A) Field of the Invention
The present invention relates to thin film transistors, and more particularly to thin film transistors of polysilicon used with liquid crystal display devices or the like.
B) Description of the Related Art
A manufacture method for a thin film transistor is known which forms a thin film transistor by crystallizing an amorphous silicon layer by applying an XeCl excimer laser beam. The diameter of polycrystalline grains formed by applying an excimer laser beam is small. A thin film transistor made of polycrystals having a small diameter has the operation performance not good. If such thin film transistors are to be used with a display device such as a liquid crystal display device, they have been used as switching transistors of a pixel display unit.
Another manufacture method for a thin film transistor is known which forms a thin film transistor by crystallizing an amorphous silicon layer by applying a continuously oscillating laser beam. The diameter of polycrystalline grains formed by applying a continuously oscillating laser beam is large. A thin film transistor made of polycrystals having a large diameter has the good operation performance. If such thin film transistors are to be used with a display device such as a liquid crystal display device, they have been used as transistors of a peripheral circuit.
In order to have a large crystal grain diameter, it is necessary to make an amorphous silicon layer have some thickness. For example, if a thickness of an amorphous silicon layer is 100 nm or thinner, it is difficult to form polycrystals having an average crystal grain diameter of 1 μm or larger. The following methods have been used in order to thin an amorphous silicon layer.
FIG. 3 is a schematic cross sectional view illustrating one process of a conventional method of manufacturing a thin film transistor. Formed on a glass substrate 50 are a buffer layer 51, an absorption film 52, an interlayer film 53 and an amorphous silicon layer 54 stacked in this order from the bottom. For example, the buffer layer 51 is made of SiO2, the absorption layer 52 is made of super elastic material such as Ti-15 Mo 0.18-O and has a thickness of 150 to 200 nm, the interlayer film 53 is made of SiO2 and has a thickness of 200 nm, and the amorphous silicon layer 54 has a thickness of 50 nm.
A continuously oscillating Nd:YAG laser beam (wavelength: 1064 nm), for example, is applied to the surface of the amorphous silicon film 54 of the structure shown in FIG. 3, to heat the absorption layer 52. By utilizing heat in the absorption film 52, the amorphous silicon film 54 is crystallized.
After the amorphous silicon film 54 is crystallized by utilizing heat in the underlying absorption film 52, a gate insulating film and a gate electrode are formed. Then, source/drain ion implantation and LDD ion implantation are performed. An interlayer insulating film and source/drain electrodes are thereafter formed (for example, refer to Japanese Patent Laid-open Publication No. 2002-50576).
FIG. 4 is a schematic perspective view partially broken and showing an example of a liquid crystal display device using polysilicon thin film transistors. Liquid crystals 74 are held between a TFT array substrate 73 formed with thin film transistors and an opposing substrate 77 formed with a common electrode. The TFT array substrate 73 has a pixel display unit 76 and a peripheral circuit unit 75 formed in a peripheral area of the pixel display unit 76 for controlling the pixel display unit 76. Polarizing plates 72 and 78 are disposed sandwiching the TFT array substrate 73 and opposing substrate 77.
On the back of the polarizing plate 72 (on the side of the plate 72 opposite to the liquid crystals 74), a back light 71 is mounted. Leak current caused by light from the back light 71 flows in polysilicon thin film transistors on the TFT array substrate 73. Leak current becomes large as the active layer of a transistor becomes thick. Transistors having leak current larger than a certain amount cannot be used in practice.
A known method of reducing leak current forms offset or LDD regions. In this case, the transistor operation speed is limited. This approach is therefore unsuitable for transistors of a peripheral circuit.